1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to an integration technique for semiconductor chips.
2. Description of the Background Art
As information devices and the like have acquired higher functionality in recent years, the demand for integration of semiconductor devices is increasing. One of the integration techniques of semiconductor devices is lamination of a plurality of semiconductor chips.
FIG. 6 is a cross-sectional view for describing a conventional first semiconductor device. Specifically, FIG. 6 shows a conventional multilayer chip module.
In FIG. 6, reference numeral 2 denotes a first semiconductor chip; 3 a second semiconductor chip; 4 a pad electrode; 7 sealant; 10 an island; 11 a wiring member; and 12 a lead.
In the conventional first semiconductor device shown in FIG. 6, two semiconductor chips 2 and 3 of different sizes are laminated on the island 10. The pad electrodes 4 of the semiconductor chips 2 and 3 are wired to the leads 12 using wiring members 11 such as gold wires. Furthermore, the conventional first semiconductor device is molded with the sealant 7 made of resin or the like except for certain portions of the leads 12.
However, the semiconductor device shown in FIG. 6 suffers from a structural restriction due to its wiring configuration. Specifically, the pad electrodes 4 on the first semiconductor chip 2 must be exposed outside, that is, they should not be covered by the back surface of the second semiconductor chip 3.
This means that it is difficult to laminate semiconductor chips of a same size. In addition, the position on the semiconductor chip at which each pad electrode 4 is formed is restricted to, for example, the outer regions of the semiconductor chip.
To solve the above problems, the semiconductor device shown in FIG. 7 was proposed. FIG. 7 is a sectional view of a conventional second semiconductor device. Specifically, FIG. 7 shows the layered structure of semiconductor chips disclosed in Japanese Patent Laid-Open No. Hei 6-21329.
In the conventional second semiconductor device shown in FIG. 7, two wiring films 13 each have bump electrodes 6 on its front and back surfaces on which semiconductor chips 2 and 3 are disposed, respectively, through the bump electrodes 6. The wiring films 13 are connected to leads 12. Furthermore, the conventional second semiconductor device is molded with the sealant 7 made of resin or the like except for certain portions of the leads 12. This arrangement realizes lamination of semiconductor chips with ease.
However, the structure shown in FIG. 7 inevitably leads to a semiconductor device of large dimensions since it is necessary to connect the wiring films 13 with the leads 12.
Furthermore, when the module molded in the sealant 7 is mounted on a substrate (not shown), it is necessary to wire the leads 12 to the substrate. This further increases the dimensions of the semiconductor device.
Thus, with the conventional semiconductor devices described above, it is not possible to miniaturize the packages and enhance semiconductor chip density.
Before the module is molded, the bump electrodes 6 and the pad electrodes 4 are positioned (but not fixed) so that the bump electrodes 6 are in contact with the pad electrodes 4. This means that it is necessary to mold the module to fix the contacting position.
Furthermore, when the module is molded, the wiring film 13 might be unintentionally shifted, resulting in misalignment of the pad electrodes 4 with the bump electrodes 6. This reduces the reliability of the semiconductor device.
The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful semiconductor device.
A more specific object of the present invention is to mount semiconductor chips on a substrate with high chip-density and to laminate a plurality of semiconductor chips without molding the module.
The above object of the present invention is attained by a following semiconductor device.
According to a first aspect of the present invention, the semiconductor device comprises: a substrate; a first semiconductor chip disposed on the substrate, the first semiconductor chip having a first electrode on a main surface thereof; a first wiring disposed on the substrate so as to cover the first semiconductor chip, the first wiring electrically connecting the first electrode to the substrate; a second semiconductor chip disposed on the first wiring, the second semiconductor chip having a second electrode on a main surface thereof, the main surface being opposite to another surface which contacts with the first wiring; and a second wiring disposed on the substrate so as to cover the second semiconductor chip and the first semiconductor chip, the second wiring electrically connecting the second electrode to the substrate.
According to a second aspect of the present invention, the semiconductor device comprises: a substrate; a first semiconductor chip disposed on the substrate, the first semiconductor chip having a first electrode on a main surface thereof; a wiring disposed on the substrate so as to cover the first semiconductor chip, the wiring electrically connecting the first electrode to the substrate; and a second semiconductor chip disposed on the wiring, the second semiconductor chip having a second electrode on a main surface thereof; the main surface of the second semiconductor chip facing the main surface of the first semiconductor chip.
According to a third aspect of the present invention, the semiconductor device comprises: a first semiconductor chip having a first electrode on a main surface thereof; a wiring disposed on the first semiconductor chip so as to be in close contact with the main surface of the first semiconductor chip, the wiring electrically connecting the first electrode to the substrate; a second semiconductor chip disposed on the wiring, the second semiconductor chip having a second electrode on a main surface thereof, the main surface of the second semiconductor chip facing the main surface of the first semiconductor chip and being in close contact with the wiring; and a sealant sealing the first semiconductor chip and the second semiconductor chip.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.